Fall 2018 Weekly Reports

Week 1 (August 26th – September 1st)

Agenda:

1. Discuss team charter and everyone’s responsibilities
   a. Get an understanding of what Advisor expects of us
2. Get feedback on supplies we will need for the project
3. Develop a projected timeline of project milestones
4. Determine which setbacks from similar projects in the past might apply to us
5. Discuss expectations for the weekly status report

Minutes:

• Start with block diagram:
  • Inputs/outputs
  • Each piece like we did in Verilog
• Keep track of 2 players.
• Bottom to choose which screen you see (your screen or theirs)
• Light to show who’s turn it is
• Give Advisor early enough so she can edit it
  • Send a week before the due date. (get first draft 2 weeks from tomorrow 8/30/2018)
• Weekly Status Reports: write it after Thursdays meetings and then give to her to edit before submitting on Mondays
  • What progress made
  • What challenge faced
  • Theoretically and physically how we progressed
  • What we plan to work on next week
• Have what exactly our MOSIS chip with process and PI so we can draw it out on the board next Thursday
• Went over all the different roles and tasks that are listed in the Project Tasks List document
• Wait until later to order other supplies.

Progress Report:

This week was the first week of school so we achieved mainly managerial tasks. We went over our team charter that was drafted in the spring, discussed more specifically who would be in charge of what tasks, and developed a list of questions we wanted to ask our advisor about the capstone process. Our goal for next week is to develop a block diagram outlining the inputs and outputs of our design. This included the MOSIS chip, raspberry pi, and LED matrix interfacing.

 

Week 2 (September 2nd – 8th)

Agenda:

1. Present our block diagram of project design to Dr. Mansouri
2. Run through how the game will be played
   a. Inquire if there are any other inputs or outputs that have been missed
3. Inquire about BOM from last year (Oscillator)
4. Discuss who to ask to be our Industry Adviser

Minutes:

• Come up with a name for the functionality of the MOSIS chip
• Neutral color for when ship or attack is moving around the board
• Mux chooses location and select
  • Keep the move button active so the player can play around with it
• The cursor will start at 0,0 when you reset it or starts from the same place you were previously
• Will need to completely slow down the clock for the 4/way button for moving
  • Can use d-ff in the MOSIS with the clock as the D to slow it down
• Pi will keep track of the location of the ship
• Put ships on board in order: 5,4,3,3,2 (horizontal by default maybe?)
• Be able to move ships after you place them (think about it)
  • Have an undo button??
  • Have a button for each ship so you can pick one to move
  • Rotates it from the lowest left corner –> what if the rotation would go out of bounds? –> figure out the math on pi to make sure it won’t move
    • Or have extra space and make the ship turn red when it rotates or moves out of bounds and make the player move it again to place it
  • Check that we have enough pins
    • Sel and rotate directly to Pi
    • 7bits instead of 8 for location
  • What information are we sending to the Pi
    • Send it serially? –> look into this to save pins

Progress Report:

This past week we created our block diagram of Input/Outputs, decided on most of the functionality of how the game would be played, and also got the website up and running. We also began brainstorming what we would need to build our design, in terms of the Build of Materials. Our goal for next week is to create the first set of FSM diagrams for the MOSIS chip logic. We also planned to add more information to the website, further look into the materials we would need, and start looking into creating our functional spec document.

 

Week 3 (September 9th – 15th)

Progress Report:

We did not have a meeting with our advisor this past week because our advisor was out sick, and we were mainly focused on finalizing more of our designs. We make more progress on our FSM’s by translating them into Verilog code to begin testing the functionality. We also designed the location calculation object for when a player will be placing their ships. The team leader started creating a milestone calendar that will be used to help the team stay on track for the rest of the semester. Lastly, we made progress on our functional spec document and divided up the sections for each of us to work on individually. Our goals for this upcoming week is to finish the first draft of our function spec document, continue design more of the game logic that will be on our MOSIS chip, and translate our location calculation design into Verilog.

 

Week 4 (September 16th – 22nd)

Agenda:

• Discuss Functional Spec Document Draft
• Present our location calculation diagram
• Discuss the budget proposal
• Dropping Translator

Minutes:

• Convey how complex this design is and how this technology can be used (School requirements)
  • How can we say this is a technology that can be used in different applications?
  • Convey what design skills it exercised and how much effort we went through
• “Master Controller” for MOSIS chip
• For Budget Proposal
  • Make sure to put a cushion in our budget
  • Advisor approves us going over $400 budget limit
• Goals: do rotate logic, code move and rotate logic and other FSM’s in Verilog (behaviorally), do some basic tests to make sure they are functional

Progress Report:

This past week the team worked hard to create the first draft of our Functional Specification Document. This included the main requirements of our project, budget, user interface, as well as many other details about our project. We were able to fill out most of the content and then sent it to our faculty advisor to review. In addition to this, we worked towards refining the move location calculation logic we started working on last week and also updated our high-level block diagram by doing further research into the parts we would need to be using. This is still a work in progress as there are still some unknowns with how the Raspberry Pi’s will interface with the MOSIS chip (Game Logic Controller) and the LED Matrices. One major decision we came to this week was to drop the Synthesized Verilog to EDIF Translator from our task list. We determined this was too much additional work for the time we have left in the semester, and it would be more time efficient to code our Verilog structurally so it will be easy to translate the design to B2Spice for the fabrication process.

Our goals for this next week are geared towards finalizing more of our logic and design of the Game Logic Controller. This will include finalizing the move location calculation logic, as well as starting and finalizing the rotating location logic and then coding them both in Verilog behaviorally to test the functionality. We would also like to code and test the other 3 FSM’s we created in Week 3. Another task for this week would be for one member to start researching how to code the Rasberry Pi in python, including how to interface with the LED and the MOSIS chip. It would be ideal to have some test code in the next few weeks. The last task for this week is going to be revising and adding content to our Functional Specification Documentation so we can put it through a second round of feedback.

 

Week 5 (September 23rd – 29th)

Agenda:

• Get feedback on functional spec document
• Discuss Verilog Design progress
  • Any questions that arise during the design session before the meeting
• Get FPGA for Shiley 306
• Inquire about industry adviser and second draft

Minutes:

• Advisor will read Functional Spec tonight and try to email us some feedback tonight/tomorrow.
• Went over how the design process has been
  • When breaking up FSM’s there is always a limit… Don’t make an excessive number of FSM’s cause you may introduce unwanted errors
  • Showed Dr. Mansouri what parts of our design we have implemented in Verilog
  • Need to set up another meeting with her to go over more in depth on the move and rotate logic.
  • Take one part of our design and take it down to the layout level (have this for next meeting with her) –> this is designing “vertically” instead of “horizontally”
    • Move logic?
    • one of the other FSM’s, etc.
  • She plans to follow up with the previous individual she contacted as well as her husband to find us a Designer in Industry to be our advisor.
  • Create the skeleton of our Design Document
    • List out all our FSM’s
    • List all the data path modules as well
    • Block Diagram of each FSM with what goes where.

Progress Report:

During this past week, we were successful in finalizing both the move location logic and the rotate logic. The structure gate/module level of this logic can be found under the Design Document Tab of this website. We were also able to start implementing the move and rotate logic in Verilog as well as go over the Main, setup, and gameplay FSM’s. Matt was able to start looking into python and how to work with the Rasberry Pi while Erik and Kristin were working on the chip design. The last big task we completed this week was our Late September Project Review, where created slides and presented to our EE capstone class on what our project was, what we had gotten done so far, and other information about where we were heading. We got some good feedback from this presentation which included updated our user interface figures to make it clear there is an LED matrix on each side of the case, as well as setting a deadline for our macro model and adding to our milestone chart.

For this next week, we plan to continue working on implementing the Verilog code of our FSM’s and move/rotate logic. It would be nice to have this completely implemented by fall break. By our advising meeting on Thursday, we plan to take one part of our design (most likely the move logic) down to the layout level. This will give us a good idea of what are space is looking like and if we will be constrained with size. We still need to submit the second draft of our Functional Specification Document, but after we get some feedback we will be working on the Final Copy of this document, which is due before fall break. Lastly, Matt will continue to learn python and look into using the Raspberry Pi’s, and the whole team will work to finalize and submit the budget by the end of week 6.

 

Week 6 (September 30th – October 6th)

Agenda:

• Specific feedback on functional spec document
• Have Matt begin the Design Document
• Go over Verilog Progress
• Talk about layout and data path drawings

Minutes:

• Add an enumerated list of the steps for playing the game
• Edit the Functional Spec Document with her notes.
• DON’T clock gate
  • Everything should get the clock at the same time. Will result in fewer issues
  • Change this on the design documents and add new logic to control it, also edit Verilog code for this
• Plan to get the FSM’s all designed in Verilog by mid-Sunday and then take one of FSM’s down to L-Edit level

Progress Report:

This past week, week 6, was a slower week for our team. All three team members had various exams throughout the week which were prioritized. Even though we were busy we made progress implementing our design in Verilog, which is almost finished. During our advising meeting, we got in-depth feedback on our Functional Specification Document so we could make changes for the final draft due this upcoming Friday. We were also successful in submitting our budget Friday, Oct 5th so we can begin ordering parts once we receive our card.

This upcoming week our main goal is to complete the final revisions of our Functional Specification Document which is due Friday, Oct 12th. We will also aim to finish implementing our design in Verilog which will act as our Macro Model. Lastly, we would like to begin outlining the requirements for our design document which will be worked on primarily after fall break.

 

Week 7 (October 7th – 13th)

Progress Report:

We did not meet with our Advisor this week due to conflicting schedules and a few team member being out of town during our usual meeting time. Our main priority for this week was to edit and submit the final version of our Functional Specification Document. We were successful in editing our document, taking into account the feedback given to us by our advisor, and uploading it to our website on Friday, October 12th. In addition to this document, we were focusing on completing the Verilog implementation of our game logic controller. This was not fully completed and is a task we will need to wrap up ASAP when the team gets back from break. Lastly, we had a team member, Matt, work on outlining the beginnings of our Design Document.

The plan for when we get back from break is to kick it into high gear with the Verilog and gate level logic implementations of our design. We need to have our preliminary chip design done by October 31st to submit to Dr. Osterburt for review. This first review is to ensure we are on track to meet the size requirements of the chip and that it will synthesize properly to be shipped off for fabrication when the times comes. In addition to wrapping up the majority of the chip design, we will begin working on the contents of the Design Document. We also hope to hear about our budget so we can begin purchasing items needed to complete our project

 

Week 8 – Fall Break

 

Week 9 (October 21st – 27th)

Agenda:

• Discuss Layout Generated of Move and Rotate
• Talk about Design Report Deadlines
• Go over Verilog Code
• Discuss general milestones and timeline

Meeting Minutes:

• Things to think about in terms of chip size
  • As you add more logic the routing gets more difficult
  • Write the exact some test benches for Verilog and B2 Spice
    • Talk to Dr. Hoffbeck and see how to write B2 Spice test bench
  • When translating into the logic level have Erik write the tests we need to get and go step by step
  • Do an example of typing small design in Verilog and verifying it against the B2 spice logic layout of the same design –> in Synopsys
  • Find a good way to test step by step and determine functional equivalence of our Verilog and B2 Spice

Progress Report:

The main focus of the meeting with our advisor this week was to discuss the progress of our MOSIS design and our plans for the next few weeks. We went over our Verilog design, which is mostly completed, as well as the progress we had made on B2 Spice schematic. We also took the schematic down to layout to give us a better idea of how much space we have left on our chip. In addition to working overtime on the Verilog and B2 Spice schematic, we have started the initial draft of our design document which is due next Friday.

Our goal for this upcoming weekend is to have roughly 50-80% of our design implemented in B2 Spice as well as tested thoroughly against our Verilog code. We also need to continually bring these schematics down to layout to ensure we are fitting size constraints. By the end of the week, we need to have most of our design complete so we can give it to Dr. Osterburg to ensure we will meet the size constraints. After this, we need to make sure our design is thoroughly tested and functions exactly as we expect it to before we send it off for fabrication. We will also continue working on the draft of the design document as it is due at the end of the week.

 

Week 10 (October 28th – November 3rd)

Progress Report:

This week we were really in crunch time when it came to our MOSIS chip design. We worked all weekend and at the beginning of the week to get a B2 Spice implementation that captured the majority of our logic. We were able to thoroughly test the move_ship logic as well as the other modules, and the full schematic seems to work for the most part. We got an estimate of how much of the chip our logic will take up, and we have plenty of space to prepare. This week Matt also worked on the draft of our Design Document, but unfortunately, we did not make as much progress as we wanted to because our main focus was on the design.

Our goals for next week is to have our chip complete implemented in B2 Spice, and tested by Friday, Nov 9th as this is when we need to submit our design to Dr. Osterburg. We also need to make significant progress on our design document so that we can turn it in to our academic advisor for feedback before the final draft is due. We also need to create slides for our presentation in class on this upcoming Friday.

 

Week 11 (November 4th – 10th)

Progress Report:

There is nothing critical to report for this week. We are still working on finalizing and testing our B2Spice Schematic

 

Week 12 (November 11th – 17th)

Agenda:

• Review Verilog and B2spice timing diagrams to show they match
• Discuss the need for a handshake to verify which location is actually valid
• Discuss expectations for Design Document

Meeting Minutes:

• Look into performing a proper handshake to ensure data will be transferred correctly
  • The team is pretty positive the processing time on the pi will be much faster than the time it takes to press 2 buttons so whiles it would be ideal to have a proper handshake creating the I/O pins to do it may be more of a risk at this stage in the design
  • Think over the idea a little more because it would be nice to have it
• found another issue in our Setup player A and B FSM’s while discussing handshake
  • As it is set up now the location is being reset before the pi would have a chance to read it
  • create another sub FSM that checks if valid is high or low and in the main FSM only have it reset the location once the signal “go” drops from high to low
• Outlined which portion of the FSM had a design flaw so Dr. Mansouri could go over it and understand the issue
• Work on the design document and try to get a draft to her by next week.

Progress Report:

This week we have been working to fully test both our Verilog design and B2Spice implementation. We wrote up complete test benches that go through each player’s set up and for player A it tested the wrapping and rotating of each ship. We then completed a game making sure to test all the extra functionality (i.e. undo). We compared the waveforms of both designs side by side and determined they were the same. After we determined that what we had was functioning we started adding the fixes described above to our design. We added more logic to make sure the pi could read the location before the processing chip reset it. We are currently working to compress the location outputs from 8 bits to 7 encoded bits, which allows 4 bits to encode the states of the game, allowing more important information to be transmitted to the pi. Another way we are thinking about giving the pi more information is to drop the second valid and gameOver inputs coming from the pi, and using an external mux if needed.
Our plan for this upcoming week is to implement all the changes we have decided we need to make and do them in a manner where we are still within the size constraints. We will also be testing it thoroughly before sending it off for fabrication. We would like to get our design turned in during the middle of the week, and we think that is a goal we can reach. In addition to this, we will also be starting work on our design document.

We had the first meeting with our Industry advisor this past Friday (11/16) to go over our design and the functional spec document we created earlier in the year. While meeting with him we were able to think through some of the issues above we are trying to fix and he also offered a few other ideas we hadn’t thought of. First of all, he said we would need to add debouncing circuits for all of our buttons, which for us would be multiple D_FFs strung together and put through an AND gate (or something like this). He also helped us think of ways to add a handshake, which we may or may not implement, as well as how to justify we could get away without one.

 

Week 13 (November 18th – 24th)

Progress Report:

During this week we continued to implement the changes to our chip design as well as thoroughly test it against our Verilog and expected values. We communicated multiple times with Dr. Osterburg to ensure the changes and additions we made would still fit within the size constraints. In addition to this, we made further progress on our design document. We met after classes without academic advisor a few times to briefly discuss our plan, but due to scheduling conflicts, we did not have an official meeting.

Our plan for this upcoming week is to begin work on our poster for the Winter Showcase. We will also continue making progress on our design document if time allows. Most of our time was spent testing our chip before it was sent off to fabrication. In addition to the main chip we were sending off to MOSIS, Erik will begin designing a debouncer chip to ensure when a button is pressed it is only read as one push and not multiple button presses.

 

Week 14 (November 25th – December 1st)

Agenda:

• Discuss the status of the design document
• Look over Poster for Showcase

Meeting Notes:

• its ok to put the design document on the back burner due to the MOSIS deadline and the need to focus time on the poster
• In terms of the poster make sure it has lots of images, diagrams, and is colorful.
  • don’t make it too wordy
  • people should be able to read everything easily and not be overwhelmed
• it would also be ideal if we started focusing more on the Raspberry Pi interface before the semester is over, so we have an idea of where we are going to start.

Progress Report:

This week Kristin spent a lot of time designing the layout of the Poster for the winter showcase. The MOSIS design was submitted and sent off to fabrication on November 28th!

For the upcoming week, the team plans to work on the design of the Poster, as well as look into the interfacing of the Pi and the fabricated chip. This will involve research and spending more time thinking about what issues we could run into next semester.

 

Week 15 (December 2nd – 8th)

Progress Report:

We did not have an official meeting this week, as it was dead week and everyone was busy preparing for finals. Kristin spent the week working on and finalizing the poster for the Winter Showcase on Friday, Dec 7th. She met with Dr. Masuoryi 2-3 times to go over the content on the paper and the visual layout. Erik worked on creating an outline of Python code towards the end of the week, and then we all did some more brainstorming about the specifics of the interfacing of our project.

Next week is finals so we are mostly done with work for the semester. The plan as of now is to be thinking about our project over the break, but overall be ready to hit the ground running once the new semester starts.